The semiconductor industry has seen tremendous advances in technology in recent years which have permitted dramatic increases in circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. Present semiconductor technology now permits single-chip microprocessors with many millions of transistors, operating at speeds of tens (or even hundreds) of MIPS (millions of instructions per second) to be packaged in relatively small, air-cooled semiconductor device packages. A by-product of such high-density and high functionality in semiconductor devices has been the demand for increased numbers of external electrical connections to be present on the exterior of the die and on the exterior of the semiconductor packages which receive the die, for connecting the packaged device to external systems, such as a printed circuit board.
Flip chip technology answers the demand for improved input/output (I/O) connections from the chip to external systems. On a flip chip, the electrical components are located (face down) on the side of the die which attaches to the chip package. In this manner, the flip chip provides a short interconnection length using, for example, ball-grid array (BGA) solder connections. The self-aligning nature of the solder bumps offers the advantages of higher density mounting, improved electrical performance and reliability, and better manufacturability. The positioning of the circuit side is the source of many advantages in the flip chip design. However, in other regards, the orientation of the die with the circuit side face down on a substrate is a disadvantage.
In example, access to the circuit region is sometimes necessitated order to modify or debug a finished chip. Additionally, access to the circuit region is often required through manufacturing stages in order to test and analyze circuit's integrity. In this event, it is necessary to burrow through the body of the flip chip die or through the chip package in order to access the circuit region.
Various methods have been employed to quickly and effectively access the circuit region. A popular method includes milling or grinding off portions of the die, or the chip packaging in order to burrow through to the circuit region. The difficulty lies in the accuracy of this method. Since the circuit region is formed in a very thin epitaxial layer, with a typical thickness of only 10-20 micrometers (.mu.m), an overshoot in the milling process can grind through the very circuit for which the testing was intended. Conversely, slowly milling off portions of the chip package is inefficient for mass fabrication procedures. For these reasons, it is necessary to have a method and device which will provide for thinning flip chip bonded integrated circuit (IC) devices with better accuracy. Likewise, a successful approach to one portion of the circuit should desirably leave other portions of the circuit intact so that they can be the subject of later analysis. Thus, to facilitate more effective and efficient back side thinning processes, a measurement method and device is accurately responsive to a desired milling depth is needed.